Package-on-package semiconductor assemblies and methods of manufacturing the same
US10381297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2018 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Jul 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.