Transistor structure and semiconductor layout structure

US10381351B2 · kind B2 · utility

Assignee

• NANYA TECHNOLOGY CORPORATION · TW

Inventors

• Ching-Chia Huang · Taipei, TW
• Tseng-Fu Lu · New Taipei, TW
• Wei-Ming Liao · Taoyuan, TW

Key dates

• Filing date: Jan 25, 2018
• Grant date: Aug 13, 2019
• Expiry date: Jan 25, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519

Abstract

The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.