Prefetching with level of aggressiveness based on effectiveness by memory access type
US10387318B2 · kind B2 · utility
2Cited by
7References
25Claims
0Family size
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Key dates
| Filing date | Dec 14, 2014 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Apr 22, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a prefetcher that prefetches data in response to memory accesses, wherein each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds scores that indicate effectiveness of the prefetcher to prefetch data with respect to the plurality of predetermined MATs. The prefetcher prefetches data in response to memory accesses at a level of aggressiveness based on the scores held in the table and the associated MATs of the memory accesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.