Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
US10387989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2017 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Jun 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5077
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for restructuring an image processing pipeline. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; or splitting the directed acyclic graph into smaller graphs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.