Methods of forming an array of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stack

US10388665B1 · kind B1 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Zhiqiang Xie · Fuzhou, CN
• Chris M. Carlson · Boise, US
• Justin B. Dorhout · Boise, US
• Anish A. Khandekar · Boise, US
• Greg Light · Meridian, US
• Ryan Meyer · Boise, US
• Kunal R. Parekh · Boise, US
• Dimitrios Pavlopoulos · Boise, US
• Kunal Shrotri · Boise, US

Key dates

• Filing date: May 30, 2018
• Grant date: Aug 20, 2019
• Expiry date: May 30, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/693
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are …