Vertical transistors with improved top source/drain junctions

US10396208B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Muthumanickam Sankarapandian · Niskayuna, US
• Ruilong Xie · Niskayuna, US
• Tenko Yamashita · Schenectady, US
• Chun-Chen Yeh · Clifton Park, US

Key dates

• Filing date: Jan 13, 2017
• Grant date: Aug 27, 2019
• Expiry date: Jan 13, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/30608
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating a top source/drain junction of a vertical transistor includes forming a structure including a bottom source/drain, a fin channel extending vertically from the bottom source/drain, and a gate arranged around the fin channel, the gate including a dielectric layer, a gate metal, and spacers arranged on top and bottom surfaces of the gate; etching to form a recess in a top surface of the fin, the recess having sidewalls that form oblique angles with respect to sidewalls of the fin; forming a top source/drain on the fin and within the recess; doping the top source/drain with a dopant; and annealing to diffuse the dopants from the top source/drain into the fin.