Two dimensional shift array for image processor
US10397450B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | May 9, 2017 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Aug 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30134
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.