Array plate short repair
US10403389B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2018 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Jun 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.