Patent · US Active

Semiconductor wafer

US10403724B2 · kind B2 · utility

0Cited by

20References

15Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Albert Birner · Regensburg, DE
Helmut Brech · Lappersdorf, DE
Simone Lavanga · Roma, IT

Key dates

Filing date	Sep 4, 2018
Grant date	Sep 3, 2019
Priority date	—
Expiry date	Sep 4, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/343
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.