Air gap spacer formation for nano-scale semiconductor devices

US10418277B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Thomas J. Haigh, Jr. · Claverack, US
• Juntao Li · Cohoes, US
• Eric G. Liniger · Danbury, US
• Sanjay C. Mehta · Niskayuna, US
• Son V. Nguyen · Irvine, US
• Chanro Park · Clifton Park, US
• Tenko Yamashita · Schenectady, US

Key dates

• Filing date: May 11, 2018
• Grant date: Sep 17, 2019
• Expiry date: May 11, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76849
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.