Split-gate flash memory cell with varying insulation gate oxides, and method of forming same
US10418451B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Aug 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a semiconductor substrate having spaced apart source and drain regions, with a channel region of the substrate extending there between, a floating gate of polysilicon disposed over and insulated from a first portion of the channel region by insulation material having a first thickness, wherein the floating gate has a sloping upper surface that terminates in a sharp edge, a word line gate of polysilicon disposed over and insulated from a second portion of the channel region by insulation material having a second thickness, and an erase gate of polysilicon disposed over and insulated from the source region by insulation material having a third thickness, wherein the erase gate includes a notch that wraps around and is insulated from the sharp edge of the floating gate. The third thickness is greater than the first thickness, and the first thickness is greater than the second thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.