Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device

US10418455B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Hui Zang · Guilderland, US
• Daniel Jaeger · Saratoga Springs, US
• Haigou Huang · Rexford, US
• Veeraraghavan S. Basker · Schenectady, US
• Christopher Nassar · Ballston Spa, US
• Jinsheng Gao · Clifton Park, US
• Michael V. Aquilino · Wappingers Falls, US

Key dates

• Filing date: Sep 26, 2017
• Grant date: Sep 17, 2019
• Expiry date: Sep 26, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.