High memory bandwidth neuromorphic computing system
US10423877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2016 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Apr 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15174
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Three-dimensional (3D) neuromorphic computing systems are provided. A system includes a logic wafer having a plurality of processors. The system further includes a double-sided interposer bonded to the logic wafer and incorporating a signal port ring for sending and receiving signals. The system also includes a plurality of 3D memory modules bonded to the double-sided interposer. The double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.