Systems and methods for selectively controlling multithreaded execution of executable code segments
US10430190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Sep 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/45
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride are disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated. For example, one or more bit of the instruction payload may be designated as a context switch bit (CTX) for expressly controlling context switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.