Arrangement and thermal management of 3D stacked dies
US10431517B2 · kind B2 · utility
4Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Aug 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.