Chip package assembly with surface mounted component protection
US10438863B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2018 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Sep 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package assembly, a package substrate and methods for fabricating the same are disclosed herein. In one example, a chip package assembly includes a package substrate, an IC die and a stiffener. The package substrate includes a first dam projecting from a top surface of the package substrate. The IC die and the stiffener are mounted to the top surface of the package substrate. The stiffener includes a bottom surface that is disposed adjacent to the first dam. At least one surface mounted component is mounted to a region of the package substrate defined between the stiffener and the IC die. An adhesive coupling the stiffener to the package substrate is in contact with the first dam.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.