Techniques for forming non-planar resistive memory cells

US10439134B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Prashant Majhi · San Jose, US
• Elijah V. Karpov · Portland, US
• Uday Shah · Portland, US
• Niloy Mukherjee · Beaverton, US
• Charles C. Kuo · Hillsboro, US
• Ravi Pillarisetty · Portland, US
• Brian S. Doyle · Portland, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Mar 25, 2014
• Grant date: Oct 8, 2019
• Expiry date: Mar 25, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8836

Abstract

Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.