Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US10446479B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Nov 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.