Integrated two-terminal device with logic device for embedded application
US10446607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2016 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Sep 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
Abstract
Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the dual damascene interconnect in the second region is coupled to the two-terminal device element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.