Asymmetric dual gate fully depleted transistor

US10446686B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Terry Hook · Jericho, US
• Kangguo Cheng · Schenectady, US
• Yi Song · Albany, US
• Chen Zhang · Guilderland, US
• Xin Miao · Guilderland, US
• Peng Xu · Guilderland, US

Key dates

• Filing date: Mar 9, 2018
• Grant date: Oct 15, 2019
• Expiry date: Mar 9, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/117

Abstract

Techniques that facilitate an asymmetric dual gate fully depleted transistor are provided. In one example, a transistor device includes a semiconductor channel structure, a first gate structure and a second gate structure. The first gate structure comprises a first length. The second gate structure comprises a second length that is different than the first length. The first gate structure is disposed on a first surface of the semiconductor channel structure and the second gate structure is disposed on a second surface of the semiconductor channel structure.