Multiple hard mask patterning to fabricate 20nm and below MRAM devices
US10446741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.