Mechanism for instruction set based thread execution on a plurality of instruction sequencers
US10452403B2 · kind B2 · utility
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21References
16Claims
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Key dates
| Filing date | Sep 26, 2015 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Sep 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.