Methods, apparatus, and manufacturing system for forming source and drain regions in a vertical field effect transistor

US10461173B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ajey Poovannummoottil Jacob · Watervliet, US
• Xuan Anh Tran · Singapore, SG
• Hui Zang · Guilderland, US
• Bala Haran · Columbia, US
• Suryanarayana Kalaga · Mechanicville, US

Key dates

• Filing date: May 25, 2018
• Grant date: Oct 29, 2019
• Expiry date: May 25, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/116

Abstract

A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.