Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures

US10461186B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• John H. Zhang · Fishkill, US
• Ruilong Xie · Niskayuna, US
• Mahender Kumar · Hopewell Junction, US

Key dates

• Filing date: May 31, 2018
• Grant date: Oct 29, 2019
• Expiry date: May 31, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76897
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate. Each VFET includes a fin extending vertically between source/drain regions, a spacer layer and a gate around the fin, and a source/drain sidewall spacer around an upper source/drain region. Optionally, a gate sidewall spacer is adjacent to the gate at a first end of the VFET. An isolation region is adjacent to the gate at a second end and opposing sides of the VFET and extends into the substrate. Contacts are formed including a lower source/drain contact (which is adjacent to the first end of the VFET and is self-aligned if the optional gate sidewall spacer is present) and a self-aligned gate contact (which extends into the isolation region at the second end of the VFET and contacts a side surface of the gate). Also disclosed are structures formed according to the methods.