High resistivity semiconductor-on-insulator wafer and a method of manufacturing
US10483152B2 · kind B2 · utility
1Cited by
23References
28Claims
0Family size
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Key dates
| Filing date | Nov 16, 2015 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Nov 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.