Transistor device structures with retrograde wells in CMOS applications

US10483172B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Vara Govindeswara Reddy Vakada · Beacon, US
• Laegu Kang · Hopewell Junction, US
• Michael Ganz · Fishkill, US
• Yi Qi · Niskayuna, US
• Puneet Khanna · Beacon, US
• Srikanth B. Samavedam · Austin, US
• Sri Charan Vemula · Clifton Park, US
• Manfred Eller · Wappingers Falls, US

Key dates

• Filing date: Oct 24, 2017
• Grant date: Nov 19, 2019
• Expiry date: Mar 1, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/859

Abstract

A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.