Overlay structures
US10483214B2 · kind B2 · utility
0Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Jan 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54466
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to semiconductor structures and, more particularly, to overlay structures and methods of manufacture. The method includes locating a first plurality of offset dummy features in a first layer; locating a second plurality of offset dummy features in a second layer; measuring a distance between the first plurality of offset dummy features and the second plurality of offset dummy features; and determining that the first layer or the second layer is shifted with respect to one another based on the measurement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.