Inventor · Rexford, NY, US

Xintuo Dai

21Patents
4h-index
48Co-inventors
55Inventor score

Filing activity: Nov 20, 2013 → Dec 23, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US9620380B1 Methods for fabricating integrated circuits using self-aligned quadruple patterning Electricity 12 Active
US9991361B2 Methods for performing a gate cut last scheme for FinFET semiconductor devices Electricity 9 Active
US10705435B2 Self-referencing and self-calibrating interference pattern overlay measurement Physics 6 Active
US10635007B1 Apparatus and method for aligning integrated circuit layers using multiple grating materials Electricity 5 Active
US10062772B2 Preventing bridge formation between replacement gate and source/drain region through STI structure Electricity 4 Active
US9812324B1 Methods to control fin tip placement Electricity 4 Active
US9329495B2 Overlay metrology system and method Physics 2 Active
US11675277B2 Self-referencing and self-calibrating interference pattern overlay measurement Physics 1 Active
US9606432B2 Alternating space decomposition in circuit structure fabrication Physics 1 Active
US9780002B1 Threshold voltage and well implantation method for semiconductor devices Electricity 1 Active
US9640402B1 Methods for gate formation in circuit structures Electricity 1 Active
US9698018B1 Introducing self-aligned dopants in semiconductor fins Electricity 1 Active
US9329471B1 Achieving a critical dimension target based on resist characteristics Physics 1 Active
US9947545B2 Methods for gate formation in circuit structures Electricity 0 Active
US10504851B2 Structure and method to improve overlay performance in semiconductor devices Electricity 0 Active
US10056458B2 Siloxane and organic-based MOL contact patterning Electricity 0 Active
US10483214B2 Overlay structures Electricity 0 Active
US10809633B1 Overlay control with corrections for lens aberrations Physics 0 Active
US11231654B2 Self-referencing and self-calibrating interference pattern overlay measurement Physics 0 Active
US10833022B2 Structure and method to improve overlay performance in semiconductor devices Electricity 0 Active
US9627274B1 Methods of forming self-aligned contacts on FinFET devices Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.