Split-gate flash cell formed on recessed substrate

US10497710B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Sung-Taeg Kang · Austin, US
• James Pak · Sunnyvale, US
• Unsoon Kim · San Jose, US
• Inkuk Kang · San Jose, US
• Chun Chen · San Jose, US
• Kuo-Tung Chang · Saratoga, US

Key dates

• Filing date: Oct 12, 2017
• Grant date: Dec 3, 2019
• Expiry date: Oct 12, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/696

Abstract

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel to the first surface, and top surfaces of the select gate and memory gate are approximately at or below an elevation of the planarized surface of the metal-gate. Generally, at least one of the top surfaces of the select gate or the memory gate includes a silicide formed thereon. Other embodiments are also disclosed.