Memory arrays
US10497715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2018 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Apr 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02255
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.