Memory elements having conductive cap layers and methods therefor
US10497868B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Apr 6, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Apr 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.