Virtual linebuffers for image signal processors
US10516833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2019 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Apr 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.