Extend GPU/CPU coherency to multi-GPU cores

US10521349B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Chandrasekaran Sakthivel · Cupertino, US
• Prasoonkumar Surti · Folsom, US
• John C. Weast · Portland, US
• Sara S. Baghsorkhi · San Jose, US
• Justin E. Gottschlich · Santa Clara, US
• Abhishek R. Appu · Cameron Park, US
• Nicolas C. Galoppo Von Borries · Portland, US
• Joydeep Ray · Folsom, US
• Narayan Srinivasa · Thousand Oaks, US
• Feng Chen · Shanghai, CN
• Ben J. Ashbaugh · Folsom, US
• Rajkishore Barik · Santa Clara, US
• Tsung-Han Lin · Campbell, US
• Kamal Sinha · Rancho Cordova, US
• Eriko Nurvitadhi · Beaverton, US
• Balaji Vembu · Folsom, US
• Altug Koker · Cameron Park, US

Key dates

• Filing date: Feb 15, 2019
• Grant date: Dec 31, 2019
• Expiry date: Feb 15, 2039

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.