Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same
US10522522B2 · kind B2 · utility
1Cited by
1References
3Claims
0Family size
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Key dates
| Filing date | Aug 1, 2016 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Aug 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor package according to the present invention comprises: an integrated substrate; a bottom chip stack, which is mounted on the integrated substrate, has multiple memory semiconductor dies stacked chip-on-chip, and takes charge of a part of the whole memory capacity; at least one top chip stack, which is mounted on the bottom package, has multiple memory semiconductor dies mounted therein, and takes charge of the rest of the whole memory capacity; an integration wire for electrically connecting the bottom chip stack and the top chip stack(s); and an integration protection member for sealing the integration wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.