Semiconductor device with air-spacer
US10522642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Jun 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.