Liner layer for dielectric block layer

US10522754B2 · kind B2 · utility

Assignee

• CrossBar, Inc. · US

Inventors

• Sundar Narayanan · Santa Clara, US
• Zhen Gu · Los Angeles, US
• Natividad Vasquez · San Francisco, US

Key dates

• Filing date: Apr 5, 2017
• Grant date: Dec 31, 2019
• Expiry date: Apr 5, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/841

Abstract

Two-terminal memory devices can be formed in part within a dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of metal particles employed in integrated circuit fabrication. This dielectric material can be protected from other fabrication processes corrosive to the dielectric material (e.g., CMP, HF clean, etc) by a silicon containing liner. Use of the silicon containing liner can enable a minimum thickness of the dielectric material to be preserved and can facilitate step height differences between adjacent material surfaces that form a two-terminal memory device to be on the order of less than about five angstroms. This small step height difference, particularly when underlying a switching layer of the two-terminal memory device, can yield excellent switching characteristics.