Semiconductor device assembly with pillar array
US10529592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2017 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Dec 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.