CMOS image sensor including pixels with read circuitry having a superlattice

US10529757B2 · kind B2 · utility

Assignee

• ATOMERA INCORPORATED · US

Inventors

• Yi-Ann Chen · Campbell, US
• Abid Husain · San Jose, US
• Hideki Takeuchi · Sakaki, JP

Key dates

• Filing date: Dec 15, 2017
• Grant date: Jan 7, 2020
• Expiry date: Dec 15, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/014

Abstract

A CMOS image sensor may include an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.