Extension region for a semiconductor device

US10529830B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Kandabara Tapily · Mechanicville, US
• Jeffrey Smith · Clifton Park, US
• Nihar Mohanty · Clifton Park, US
• Anton J. deVilliers · Boise, US

Key dates

• Filing date: Aug 10, 2017
• Grant date: Jan 7, 2020
• Expiry date: Aug 10, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/666
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A method of forming a semiconductor device having a channel and a source-drain coupled to the channel. The method includes etching a channel region such that an end of the channel region forms a recess within a gate structure surrounding the channel region. An extension region is formed in contact with the channel region and at least partially filling the recess. Extension material of the extension region has a different composition from channel material of the channel region such that a strain is caused in the channel region. A source-drain region is in contact with the extension region and adjacent to the gate structure.