Multi-metal fill with self-aligned patterning and dielectric with voids
US10534273B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | May 4, 2017 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | May 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76849
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.