Sensing techniques for multi-level cells
US10535397B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Aug 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for sensing a memory cell configured to store three or more states. A charge may be transferred between a digit line and a node coupled with a sense component using a charge transfer device. During a single read operation, multiple voltages may be applied to the gate of the charge transfer device. The node may be sensed a number of times based on a number of voltages applied to the gate of the charge transfer device. The charge may be transferred by the charge transfer device based on a value of the signal on a digit line and a voltage applied to the gate of the charge transfer device. Based on the charge being transferred and the sense component sensing the node multiple times, a logic state associated with the memory cell may be determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.