Memory cells with enhanced tunneling magnetoresistance ratio, memory devices and systems including the same
US10541014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2015 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Dec 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5615
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.