Convolutional neural network on programmable two dimensional image processor
US10546211B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2016 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | May 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/20084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The two-dimensional shift register provides local respective register space for the execution lanes. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.