Method to reduce trap-induced capacitance in interconnect dielectric barrier stack

US10546742B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• He Ren · San Jose, US
• Mehul Naik · San Jose, US
• Yong Cao · Goleta, US
• Yana Cheng · San Jose, US
• Weifeng YE · San Jose, US

Key dates

• Filing date: Dec 31, 2018
• Grant date: Jan 28, 2020
• Expiry date: Dec 31, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76832
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.