Field-effect transistors with improved dielectric gap fill
US10546775B1 · kind B1 · utility
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19Claims
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Key dates
| Filing date | Aug 1, 2018 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Aug 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/792
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.