Patent · US Active

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US10552357B2 · kind B2 · utility

12Cited by

2References

25Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Zuoguo Wu · San Jose, US
Mahesh Wagh · Portland, US
Debendra Das Sharma · Saratoga, US
Gerald Pasdast · San Jose, US
Ananthan Ayyasamy · Bengaluru, IN
Xiaobei Li · Sammamish, US
Robert G. Blankenship · Tacoma, US
Robert J. Safranek · Portland, US

Key dates

Filing date	Nov 22, 2017
Grant date	Feb 4, 2020
Priority date	—
Expiry date	Nov 22, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.