Static random access memory structure
US10559573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Oct 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.