Selector device having asymmetric conductance for memory applications
US10559624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2017 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Sep 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/245
Abstract
The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element, which has a low resistance state and a high resistance state, and a two-terminal selector coupled to the MTJ memory element in series. The MTJ memory element includes a magnetic free layer and a magnetic reference layer with an insulating tunnel junction layer interposed therebetween. The two-terminal selector has an insulative state and a conductive state. The two-terminal selector in the conductive state has substantially lower resistance when switching the MTJ memory element from the low to high resistance state than from the high to low resistance state. The voltages applied to the memory cell to respectively switch the MTJ memory element from the low to high resistance state and from the high to low resistance state may be substantially same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.