Transistor device and semiconductor layout structure including asymmetrical channel region
US10559661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Jan 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes an active region disposed in a substrate, a gate structure disposed over the active region, and a source/drain region disposed at two opposite sides of the gate structure. The active region includes a first region including a first length, a second region including a second length less than the first length, and a third region between the first region and the second region. The gate structure includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction. The first portion is disposed over at least the third region of the active region, and the second portion is disposed over at least a portion of the third region and a portion of the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.