Pessimism reduction in cross-talk noise determination used in integrated circuit design
US10565336B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | May 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to perform an integrated circuit design involves selecting a net among a plurality of nets of the integrated circuit design as a victim net. Each net connects a pair of nodes of the integrated circuit design and each node represents a logic element of the integrated circuit design. The method also includes determining aggressor nets among the plurality of nets for the victim net and determining a corresponding weight value for each of the aggressor nets and, for each of the aggressor nets, multiplying the coupled noise originating from the aggressor net with the corresponding weight value to obtain a weighted coupled noise value. A cumulative coupled noise value is obtained for the victim net as a sum of the weighted coupled noise values associated with each of the aggressor nets. A result of the integrated circuit design is provided for fabrication into an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.